From a review of the hardware guide, and otherwise given the fact that the on-board DDR ram appears to be integrated into the SoC, am I correct in understanding that there is no direct means to access the on-board ram without the use of translation/transmission through a standard protocol channel? If so, does the SoC have any otherwise 'unmentioned' capability (i.e. a memory controller) to directly address/manage additional/external DDR chips? For my particular application I am considering a situation, as in motion-vision-response, in-conjunction with a FPGA or similar which for best results, once the 'processing' was completed, allow such an external IC to proceed as close in step with the processor as possible without the additional lag time of having to 'off-load' the memory contents which is otherwise constrained by the bus speed and number of channels available.
↧